Stacked semiconductor dies are used in a wide variety of applications that require high data transfer rates and/or small footprints. For example, many systems require a processor die (e.g., logic die) and one or more memory dies. Traditionally, the processor and memory dies are packaged in separate packages and are electrically interconnected through a motherboard. In some applications, the processor and memory dies are placed next to each other on a common packaging substrate that provides electrical connectivity between the processor and memory dies. Nonetheless, in such applications a relatively large distance from one die to another limits the data transfer rates among the dies. The data transfer rates are additionally limited by the capacitance and inductance of the traces that electrically interconnect the dies. Furthermore, each die (e.g., a processor or a memory die) occupies space on the substrate in proportion to its size and to the corresponding traces that connect the die to other dies, such that side-by-side configurations have larger overall footprints.
For applications that require higher data transfer rates and/or smaller packages, a processor and several memory dies can be stacked vertically and electrically interconnected using TSVs. The TSVs enable stacked dies to be stacked close to each other such that the dies are spaced apart from each other by only relatively small vertical distances, which in combination with the relatively low inductance of the TSVs enables higher data transfer rates. Also, since the dies are stacked vertically, the total footprint of the stack corresponds to the footprint of the largest die in the stack.
FIG. 1 is a partially schematic cross-sectional view of a vertically stacked die arrangement in accordance with the prior art. As shown in FIG. 1, a stacked die assembly 1000 has a processor die 110, three memory dies 120a-c stacked on the processor die 110, and TSVs 150 that electrically connect the processor die 110 with the memory dies 120a-c. The processor die 110 can have several functional areas, for example a processor core 116, read/write logic 117 and/or I/O buffer 118. These functional areas can be electrically interconnected through metallization traces 119. The processor die 110 also includes pads 115 for electrically connecting the stacked die assembly 1000 to a package substrate (not shown) through, for example, wirebonds. The closely spaced, vertically stacked dies 110 and 120a-c are suitable for relatively high data transfer rates while occupying only a relatively small total area. However, the close spacing of the semiconductor dies also increases the density of power dissipated by the semiconductor dies. Therefore, thermal management is typically more difficult for stacked semiconductor dies than for other arrangements. One possible improvement in the thermal management of the stacked semiconductor dies includes placing thermal pads (dummy pads, outrigger pads) between the dies in the stack to enhance heat transfer through and ultimately out of the stack.
FIGS. 2A-2G illustrate a manufacturing process for thermal pads of a semiconductor die stack in accordance with the prior art. FIG. 2A illustrates a semiconductor die 201 attached to a carrier wafer 225 by an adhesive 220. The carrier wafer 225 can be used to improve handling and to protect the semiconductor dies during the manufacturing process. Suitable carrier materials are, for example, ceramic or silicon. In a typical semiconductor manufacturing process, the carrier wafer will be removed from the semiconductor dies before packaging the individual semiconductor dies. The semiconductor die 201 can have a silicon material 210, an active structure 215 that includes electrical circuits, and TSVs 230 interconnecting the electrical circuits of the active structure 215 to an area at a peripheral surface 211 of the silicon material 210. As explained in relation to FIG. 2G below, the peripheral surface 211 faces additional die or dies in the stack. The die 210 can also have an isolation lining 235 (FIGS. 2A-2C) that electrically isolates a conductive material 231 of the TSV 230 from the silicon material 210. Only one TSV 230 is shown in FIG. 2A for clarity, but a typical semiconductor die would include many TSVs.
FIG. 2B illustrates the semiconductor die 201 after planarizing or grinding the peripheral surface 211. This can thin the die and roughen the peripheral surface 211, which improves adhesion of mask layers used in subsequent processing steps.
FIG. 2C illustrates the semiconductor die 201 after the peripheral surface 211 has been etched to expose one end portion of the TSV 230. Suitable silicon etching techniques include, for example, selectively etching silicon while not etching metals, for example copper. After etching, a portion of the TSV 230 projects above the peripheral surface 211 of the semiconductor die 201.
FIGS. 2D and 2E illustrate the semiconductor die 201 with a passivation material 280 before and after patterning, respectively. The passivation material 280 can be a polymer, for example, a polyimide. Suitable patterning techniques include, for example, photo patterning and developing a resist material to etch indentations 285 in the passivation material 280. For example, a leaky chrome process can be used to pattern the indentations 285. The indentations 285 in the passivation material 280 provide locations for subsequent metal deposition. For example, sputtering techniques can be used to deposit metal into the indentations 285.
FIG. 2F illustrates the semiconductor die 201 after depositing metal into the indentations 285 to form thermal pads 250 and an under-bump metallization (UBM) structure 255. The thermal pads 250 and UBM structure 255 are formed during the same metal deposition process. The thermal pads 250 have a relatively high thermal conductivity that improves heat dissipation from the semiconductor die 201 when the thermal pads 250 contact the next semiconductor die in the stack. The thermal pads 250 transfer heat through the stack and ultimately to the environment. The UBM structure 255 that caps the exposed end of the TSV 230 electrically connects signal, power and/or ground lines with other semiconductor dies in the stack. With the conventional technology, the thermal pads 250 are formed over a thin portion of the passivation material 280 that separates the thermal pads 250 from the silicon material 210 by a thickness T. Additionally, since the thermal pads 250 and UBM structure 255 are formed in a same semiconductor manufacturing step (e.g., metal deposition), approximately same thickness of material is added to the target areas of the semiconductor die corresponding to the pattern of indentations 285. As such, after forming the UBM structures 255 and the thermal pads 250, the top of the UBM structure 255 may be higher than the top of the thermal pad. For example, the top of the UBM structure 255 may be separated from the top of the thermal pad 250 by a distance L.
FIG. 2G illustrates stacking of the semiconductor dies 201 and 202 stacked after the carrier wafer 225 and adhesive 220 have been removed. The semiconductor dies 201 and 202 are aligned such that the TSV 230 of the semiconductor die 201 connects to a TSV 232 of the semiconductor die 202 through a die pad 270 when the semiconductor dies are brought into contact in a direction of arrows 251. The thermal pads 250 help to transfer heat Q from the stack in addition to the heat transferred through the TSV 230. The illustrated conventional thermal pads 250, however, suffer from several deficiencies. For example, the passivation material 280 (e.g., a polymer) has a relatively low thermal conductivity that inhibits heat transfer from the semiconductor die 202 in proportion to a thickness T of the passivation material that separates the thermal pads 250 from the silicon material 210. Furthermore, the uneven height (e.g., distance L) of the UBM structure 255 and the thermal pads 250 generally reduces the stacking yield of the semiconductor dies because contact between the UBM structure 255 and the die pad 270 can prevent the thermal pads 250 from contacting the semiconductor die 202.